Article on 3D chip design

A fluffy but kind of fun overview of constructing chips in three dimensions.  Link.  I liked the cutaway view of 8 layers of metal; kind of humbling that they can make this stuff this small and still get any kind of yield out of the process.


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0 Responses to Article on 3D chip design

  1. Davo says:

    Thanks for the link to this – back in my days doing semiconductor F/A at IBM we had 20 micron lines, two signal layers, and a power and I/O layer.

    Key to circuit density – they have solved the substrate parasitic currents to a level we could have only dreamed of ~25 years ago.

    This really is a mindblower to think they can manage yields with structures like this. Besides contamination control, proper mask registration, and the various etching techniques (reactive ion – maybe others by now), the physics (esp. the electrons and thermo) going on in there must be bizarro.
    It was weird enough in the early 1980’s!

  2. landon says:

    20 microns sounds like you could practically make that stuff in a garage, these days. (I know, not really. But NBS / NIST had a small fab in their computing division, and they probably did that there).

    My father-in-law used to work for an outfit that made steppers and other photolithography equipment. He has interesting tales to tell… 🙂

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